FIG. 1 shows a typical modern computer system 100 which can include one or more processors modules 110, a memory module 120, and input/output (I/O) modules 130. In this, as well subsequent figures, the broken lines generally indicate physically discrete components. Each processor module 110 can include a central processor unit (CPU) 111, a cache 112, and a cache controller (CACHE CTRL) 113 connected to each other by a CPU bus 114 internal to the processor module 110. A memory 121 of the memory module 120 is usually implemented using a plurality of memory cards 122, e.g., "SIMMS," coupled by a memory bus 124. The I/O modules 130 include I/O interfaces 131 for connecting to I/O devices 132, such as disks, tapes, printers, terminals, and so forth, and I/O controllers (I/O CTRL) 133.
A back-plane, or, as it is commonly known in computers of more recent design, a mother-board, 140 provides the physical and electrical coupling for the "daughter" modules 110, 120, and 130. The physical coupling is provided by edge connectors or "slots" 150 mounted on one side surface 149 of the mother-board 140. The slots 150 can receive the modules 110, 120, and 130. The slots can be individually configured to receive modules having different physical and electrical characteristics.
The electrical coupling between the modules 110, 120, and 130 is provided by communication buses 161-163. The communications buses 161-163 include, respectively, signaling paths 141-143 for data, address, and control signals. The signaling paths are usually physically integrated into the mother-board 140, and are connected to pins of the slots 150. Each of the signaling paths 141-143 can include a plurality of electrically conductive lines, not shown. For example, the signalling path 141 used for data signals may include thirty-two lines, and, perhaps, additional parity lines.
In most computer systems, the communications buses 161-163 include a proprietary processor bus 161 for coupling the processor and memory modules. In addition, industry standard I/O buses 162-163 can be used to couple the I/O modules. For example, the I/O buses 162-163 can, respectively, be compatible with the industry PCI and EISA standards.
A bridge 170, physically integrated into the mother-board 140, and directly connected to the processor and I/O bus, provides the interface between signals of the proprietary processor bus 161 and the industry standard PCI bus 162. A second bridge 171 may be used to couple the PCI bus 162 with the EISA bus 163.
It is understood that the configuration of the proprietary processor bus 161 can vary for different processor architectures, or for that matter, for processors of the same architecture, but different manufacturing sources. For example, the number of signaling lines or "width" of the bus can vary. Obviously, a 64-bit system would have about twice as many data and address lines as a 32-bit system.
In addition, the allocation and relative physical position of the lines on the pins of the slots 150 for data, address, and control lines 141-143 can vary. There can also be variations in signaling levels, signaling frequency, and bus protocols. For example, the bus protocols used in a processor of a RISC design may be quite different than the bus protocol used in a processor using a CISC design.
In other words, in traditional computer systems, the design of the mother-board 140, and, more particularly, the design of the proprietary processor bus 161 is dictated by specific processor architectures. Once the architecture has been selected the configuration of the signaling paths 141-143 of the proprietary processor bus 161 is fixed.
For example, consumers buying a computer system having a mother-board configured to receive INTEL "x86" type of processors modules using the 32-bit CISC architecture operating at 30 MHz, would realize that they probably would not be able upgrade their machine, without considerable expense, to receive a more powerful and faster INTEL "PENTIUM" (Tm) type of processor module. Upgrading their computer system to a totally different architecture using, for example, a 64-bit, 200 MHz, "ALPHA" processor from Digital Equipment Corporation, using the RISC architecture, would be beyond consideration. Needless to say, upgrading the system to 128-bit architectures of the future would be practically impossible.
Therefore, it would be an advantage if a computer system could be equipped with a mother-board that is adaptable to different processor architectures. A mother-board which can receive 32-bit CISC processors one day, and 64-bit RISC processors another day, and some day in the future, capable of receiving a 128-bit processors of a yet to be designed architecture would be a preferred consumer choice. Thus, it is desired to adapt computer systems to different processor architectures without substantially increasing the cost or complexity of the system.